SherbyNet - /page/wikibook/entry.mu

Micron Document

<!DOCTYPE html>

<title>Asynchronous system</title>

</head>

<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Asynchronous system</span></span>

</h1>

</header>

/* start https://en.wikipedia.org/ */

.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}

/* end https://en.wikipedia.org/ */

</style><div role="note" class="hatnote navigation-not-searchable">For additional information, see <a href="Asynchronous_circuit" title="Asynchronous circuit">Asynchronous circuit</a>.</div>

/* start https://en.wikipedia.org/ */

.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}

/* end https://en.wikipedia.org/ */

</style>

<p>The primary focus of this article is asynchronous control in digital electronic systems.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> In a <a href="Synchronous_system" class="mw-redirect" title="Synchronous system">synchronous system</a>, operations (<a href="Machine_code" title="Machine code">instructions</a>, <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">calculations</a>, <a href="Sequential_logic" title="Sequential logic">logic</a>, etc.) are coordinated by one, or more, centralized <a href="Clock_signal" title="Clock signal">clock signals</a>. An <b>asynchronous system</b>, in contrast, has no global clock. Asynchronous systems do not depend on strict arrival times of signals or messages for reliable operation. Coordination is achieved using <a href="Event-driven_architecture" title="Event-driven architecture">event-driven architecture</a> triggered by <a href="Network_packet" title="Network packet">network packet</a> arrival, changes (transitions) of signals, handshake protocols, and other methods.

</p>

<div class="mw-heading mw-heading2"><h2 id="Modularity">Modularity</h2></div>

<p>Asynchronous systems – much like <a href="Object-oriented_programming" title="Object-oriented programming">object-oriented</a> software – are typically constructed out of <a href="Module_(programming)" class="mw-redirect" title="Module (programming)">modular</a> 'hardware objects', each with well-defined communication <a href="Interface_(computer_science)" class="mw-redirect" title="Interface (computer science)">interfaces</a>. These <a href="Modularity_(programming)" class="mw-redirect" title="Modularity (programming)">modules</a> may operate at variable speeds, whether due to data-dependent processing, <a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">dynamic voltage scaling</a>, or <a href="Process_variation" class="mw-redirect" title="Process variation">process variation</a>. The modules can then be combined to form a correct working system, without reference to a global <a href="Clock_signal" title="Clock signal">clock signal</a>. Typically, <a href="Low-power_electronics" title="Low-power electronics">low power</a> is obtained since components are activated only on demand. Furthermore, several asynchronous styles have been shown to accommodate clocked interfaces, and thereby support mixed-timing design. Hence, asynchronous systems match well the need for correct-by-construction <a href="Methodology" title="Methodology">methodologies</a> in assembling large-scale heterogeneous and scalable systems.

</p>

<div class="mw-heading mw-heading2"><h2 id="Design_styles">Design styles</h2></div>

<p>There is a large spectrum of asynchronous design styles, with tradeoffs between robustness and performance (and other parameters such as power). The choice of design style depends on the application target: reliability/ease-of-design vs. speed. The most robust designs use '<a href="Delay_insensitive_circuit" title="Delay insensitive circuit">delay-insensitive circuits</a>', whose operation is correct regardless

of <a href="Delay_calculation" title="Delay calculation">gate and wire delays</a>; however, only limited useful systems can be designed with this style. Slightly less robust, but much more useful, are <a href="Quasi-delay-insensitive_circuit" title="Quasi-delay-insensitive circuit">quasi-delay-insensitive circuits</a> (also known as speed-independent circuits), such as <a href="Delay-insensitive_minterm_synthesis" title="Delay-insensitive minterm synthesis">delay-insensitive minterm synthesis</a>, which operate correctly regardless of <a href="Delay_calculation" title="Delay calculation">gate delays</a>; however, wires at each <a href="Fanout" class="mw-redirect" title="Fanout">fanout</a> point must be tuned for roughly equal delays. Less robust but faster circuits, requiring simple localized one-sided timing constraints, include <a href="Microcontroller" title="Microcontroller">controllers</a> using fundamental-mode operation (i.e. with setup/hold requirements on when new inputs can be received), and bundled datapaths using matched delays (see below). At the extreme, high-performance "timed circuits" have been proposed, which use tight two-side timing constraints, where the <a href="Clock_signal" title="Clock signal">clock</a> can still be avoided but careful physical delay tuning is required, such as for some high-speed <a href="Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> applications..

</p>

<div class="mw-heading mw-heading2"><h2 id="Asynchronous_communication">Asynchronous communication</h2></div>

<p><a href="Asynchronous_communication" title="Asynchronous communication">Asynchronous communication</a> is typically performed on <a href="Communication_channel" title="Communication channel">communication channels</a>. Communication is used both to <a href="Synchronize" class="mw-redirect" title="Synchronize">synchronize</a> operations of the concurrent system as well as to pass data. A simple channel typically consists of two wires: a request and an acknowledge. In a '4-phase <a href="Handshake_(computing)" title="Handshake (computing)">handshaking</a> <a href="Protocol_(computing)" class="mw-redirect" title="Protocol (computing)">protocol</a>' (or return-to-zero), the request is asserted by the sender component, and the receiver responds by asserting the acknowledge; then both signals are de-asserted in turn. In a '2-phase <a href="Handshake_(computing)" title="Handshake (computing)">handshaking</a> <a href="Protocol_(computing)" class="mw-redirect" title="Protocol (computing)">protocol</a>' (or transition-signalling), the requester simply toggles the value on the request wire (once), and the receiver responds by toggling the value on the acknowledge wire. Channels can also be extended to communicate data.

</p>

<div class="mw-heading mw-heading2"><h2 id="Asynchronous_datapaths">Asynchronous datapaths</h2></div>

<p>Asynchronous <a href="Datapath" title="Datapath">datapaths</a> are typically encoded using several schemes. Robust schemes use two wires or 'rails' for each bit, called 'dual-rail encoding'. In this case, first rail is asserted to transmit a 0 value, or the second rail is asserted to transmit a 1 value. The asserted rail is then reset to zero before the next data value is transmitted, thereby indicating 'no data' or a 'spacer' state. A less robust, but widely used and practical scheme, is called 'single-rail bundled data'. Here, a single-rail (i.e. synchronous-style) function block can be used, with an accompanying <a href="Worst-case" class="mw-redirect" title="Worst-case">worst-case</a> matched delay. After valid data inputs arrive, a request signal is <a href="Assertion_(software_development)" title="Assertion (software development)">asserted</a> as the input to the matched delay. When the matched delay produces a 'done' output, the block guaranteed to have completed computation. While this scheme has timing constraints, they are simple, localized (unlike in <a href="Synchronous_system" class="mw-redirect" title="Synchronous system">synchronous systems</a>), and one-sided, hence are usually easy to validate.

</p>

<div class="mw-heading mw-heading2"><h2 id="Literature">Literature</h2></div>

<p>The literature in this field exists in a variety of conference and journal proceedings. The leading symposium is the IEEE Async Symposium (International Symposium on Asynchronous Circuits and Systems), founded in 1994. A variety of asynchronous papers have also been published since the mid-1980s in such conferences as IEEE/ACM <a href="Design_Automation_Conference" title="Design Automation Conference">Design Automation Conference</a>, IEEE <a rel="nofollow" class="external text" href="http://www.iccd-conference.com">International Conference on Computer Design</a>, IEEE/ACM <a href="International_Conference_on_Computer-Aided_Design" title="International Conference on Computer-Aided Design">International Conference on Computer-Aided Design</a>, <a rel="nofollow" class="external text" href="http://www.isscc.org/isscc/">International Solid-State Circuits Conference</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100316191113/http://www.isscc.org/isscc/">Archived</a> 2010-03-16 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, and Advanced Research in VLSI, as well as in leading journals such as IEEE Transactions on VLSI Systems, <a href="IEEE_Transactions_on_Computer-Aided_Design_of_Integrated_Circuits_and_Systems" title="IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a>, and Transactions on Distributed Computing.

</p>

<ul><li><a href="Design_flow_(EDA)" title="Design flow (EDA)">Design flow (EDA)</a></li>

<li><a href="Electronic_design_automation" title="Electronic design automation">Electronic design automation</a></li>

<li><a href="Integrated_circuit_design" title="Integrated circuit design">Integrated circuit design</a></li>

<li><a href="Isochronous_timing" title="Isochronous timing">Isochronous timing</a></li>

<li><a href="Mesochronous_network" title="Mesochronous network">Mesochronous network</a></li>

<li><a href="Perfect_clock_gating" class="mw-redirect" title="Perfect clock gating">Perfect clock gating</a></li>

<li><a href="Plesiochronous_system" title="Plesiochronous system">Plesiochronous system</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

/* start https://en.wikipedia.org/ */

.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}

/* end https://en.wikipedia.org/ */

</style><div class="reflist">

/* start https://en.wikipedia.org/ */

.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("./mw/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("./mw/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("./mw/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("./mw/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}

/* end https://en.wikipedia.org/ */

</style><cite id="CITEREFLosadaRubioDormido2015" class="citation book cs1">Losada, María Guinaldo; Rubio, Francisco Rodríguez; Dormido, Sebastián (2015-10-04). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=1EqGCgAAQBAJ"><i>Asynchronous Control for Networked Systems</i></a>. Springer. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>9783319212999</bdi>.</cite></span>

</li>

<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite id="CITEREFSparsøFurber2013" class="citation book cs1">Sparsø, Jens; Furber, Steve (2013-04-17). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=fefgBwAAQBAJ"><i>Principles of Asynchronous Circuit Design: A Systems Perspective</i></a>. Springer Science & Business Media. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>9781475733853</bdi>.</cite></span>

</li>

</ol></div></div>

/* start https://en.wikipedia.org/ */

.mw-parser-output .refbegin{margin-bottom:0.5em}.mw-parser-output .refbegin-hanging-indents>ul{margin-left:0}.mw-parser-output .refbegin-hanging-indents>ul>li{margin-left:0;padding-left:3.2em;text-indent:-3.2em}.mw-parser-output .refbegin-hanging-indents ul,.mw-parser-output .refbegin-hanging-indents ul li{list-style:none}@media(max-width:720px){.mw-parser-output .refbegin-hanging-indents>ul>li{padding-left:1.6em;text-indent:-1.6em}}.mw-parser-output .refbegin-columns{margin-top:0.3em}.mw-parser-output .refbegin-columns ul{margin-top:0}.mw-parser-output .refbegin-columns li{page-break-inside:avoid;break-inside:avoid-column}@media screen{.mw-parser-output .refbegin{font-size:90%}}

/* end https://en.wikipedia.org/ */

</style><div class="refbegin" style="">

<ul><li>S.M. Nowick and M. Singh, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220514002733/http://www.cs.columbia.edu/~nowick/nowick-singh-async-IEEE-DT-15-overview-article-pt1.pdf">"Asynchronous Design -- Part 1: Overview and Recent Advances"</a>, IEEE Design and Test, vol. 32:3, pp. 5–18 (May/June 2015).</li>

<li>S.M. Nowick and M. Singh, <a rel="nofollow" class="external text" href="https://wayback.archive-it.org/all/20181221132622/http://www.cs.columbia.edu/%7Enowick/nowick%2Dsingh%2Dasync%2DIEEE%2DDT%2D15%2Doverview%2Darticle%2Dpt2.pdf">"Asynchronous Design -- Part 2: Systems and Methodologies"</a>, IEEE Design and Test, vol. 32:3, pp. 19–28 (May/June 2015)

<ul><li>These two articles provide a broad and modern snapshot of the state-of-the-art of asynchronous design. They include a short history of asynchronous design, as well as a technical introduction to handshaking protocols and data encoding, hazard-free logic, and controller design. They also cover recent industrial successes in mainstream technologies (IBM, Intel, Philips Semiconductors, etc.), as well as recent application to emerging areas (neuromorphic computers, flexible electronics, <a href="Quantum_cellular_automaton" title="Quantum cellular automaton">quantum cellular automata</a>, continuous-time DSPs, ultra-low voltage design, extreme environments). Highlights several application areas in depth, with a wide range of cited publications: GALS systems, networks-on-chip, computer architecture, testing and design-for-testability, and CAD tool development.</li></ul></li>

<li>Claire Tristram, "It's Time for Clockless Chips", cover story, MIT's Technology Review Magazine, vol. 104:8, pp. 36–41, October 2001.</li>

<li>C.H. van Berkel, M.B. Josephs, and S.M. Nowick, <a rel="nofollow" class="external text" href="https://doi.org/10.1109%2F5.740016">Applications of Asynchronous Circuits</a> , Proceedings of the IEEE, Vol. 87, No. 2, pp. 223–233, February 1999. (<i>This entire issue is devoted to asynchronous circuits, with many other relevant articles</i>.)</li>

<li>L. Lavagno and S.M. Nowick, "Asynchronous Control Circuits", chapter 10 in <cite id="CITEREFeds._Soha_Hassoun_and_Tsutomu_Sasao2002" class="citation book cs1">eds. <a href="Soha_Hassoun" title="Soha Hassoun">Soha Hassoun</a> and Tsutomu Sasao (2002). <i>Logic Synthesis and Verification</i>. Kluwer Academic Publishers. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-7923-7606-4</bdi>.</cite> <span class="cs1-visible-error citation-comment"><code class="cs1-code">{{cite book}}</code>: </span><span class="cs1-visible-error citation-comment"><code class="cs1-code">|author=</code> has generic name (help)</span>, pp. 255–284,(<i>Includes pointers to recent asynchronous chips, as well as coverage of CAD techniques for asynchronous control circuits</i>.)</li></ul>

</div>

<hr>

<p>Adapted from <a rel="nofollow" class="external text" href="http://www1.cs.columbia.edu/~nowick/">Steve Nowick</a>'s column in the ACM <a rel="nofollow" class="external text" href="http://www.sigda.org">SIGDA</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070208034716/http://www.sigda.org/newsletter/index.html">e-newsletter</a> by <a rel="nofollow" class="external text" href="http://www.eecs.umich.edu/~imarkov/">Igor Markov</a> <br>

Original text is available at <a rel="nofollow" class="external free" href="https://web.archive.org/web/20060624073502/http://www.sigda.org/newsletter/2006/eNews_060115.html">https://web.archive.org/web/20060624073502/http://www.sigda.org/newsletter/2006/eNews_060115.html</a>

</p>

<hr>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="http://www.scitechinfo.com/node/638">ARM ARM996HS clockless processor</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160303212839/http://www.scitechinfo.com/node/638">Archived</a> 2016-03-03 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060620114944/http://www.na2.es/research.htm">Navarre AsyncArt. N-Protocol: Asynchronous Design Methodology for FPGAs</a></li>

<li><a rel="nofollow" class="external text" href="http://async.org.uk">Asynchronous design page at Newcastle University</a></li>

<li>Workcraft: toolset for asynchronous circuit synthesis and verification <a rel="nofollow" class="external free" href="https://workcraft.org/">https://workcraft.org/</a></li></ul></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-07-29" href="https://en.wikipedia.org/wiki/?title=Asynchronous_system&oldid=1303148558">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

</div>

</div></div>

</div>

</main>

</div>

</body></html>